Renesas R5S72621 User Manual
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 485 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
11.3.15
Timer Read/Write Enable Register (TRWER)
TRWER is an 8-bit readable/writable register that enables or disables access to the registers and
counters which have write-protection capability against accidental modification in channels 3 and
4.
counters which have write-protection capability against accidental modification in channels 3 and
4.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
R
R
R
R
R
R
R
R/W
-
-
-
-
-
-
-
RWE
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7 to 1
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
0 RWE 1 R/W
Read/Write
Enable
Enables or disables access to the registers which have
write-protection capability against accidental
modification.
write-protection capability against accidental
modification.
0: Disables read/write access to the registers
1: Enables read/write access to the registers
[Clearing condition]
When 0 is written to the RWE bit after reading
RWE = 1
Registers and counters having write-protection capability against accidental modification
22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3,
TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1,
TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT4.
TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1,
TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT4.