Renesas R5S72621 User Manual
Section 11 Multi-Function Timer Pulse Unit 2
Page 604 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
11.7.9
Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data in the buffer before input capture transfer.
be the data in the buffer before input capture transfer.
Figure 11.104 shows the timing in this case.
Input capture
signal
signal
Read signal
Address
TGR read cycle
T1
T2
TGR
Internal data
bus
TGR address
P
φ
N
N
M
Figure 11.104 Contention between TGR Read and Input Capture