Renesas R5S72621 User Manual
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 611 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
11.7.17
Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
not set and TCNT clearing takes precedence.
Figure 11.111 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
source, and when H'FFFF is set in TGR.
Counter clear
signal
signal
TCNT
TCNT input
clock
clock
H'FFFF
H'0000
TGF
TCFV
Disabled
MP
φ
Figure 11.111 Contention between Overflow and Counter Clearing