Renesas R5S72621 User Manual

 

Section 14   Realtime Clock 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 697 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

1 RESET 

0 

R/W 

Reset 

Writing 1 to this bit initializes the divider circuit, the 
R64CNT register, the alarm register, the RCR3 register, 
bits CF and AF in RCR1, and bit PEF in RCR2. In this 
case, the RESET bit is automatically reset to 0 after 1 is 
written to and the above registers are reset. Thus, there 
is no need to write 1 to this bit. This bit is always read 
as 0. 

0: Runs normally. 

1: Divider circuit is reset. 

0 START 

1 

R/W 

Start 

Halts and restarts the counter (clock). 

0: Second/minute/hour/day/week/month/year counter 

halts. 

1: Second/minute/hour/day/week/month/year counter 

runs normally. 

 

When the ENB bit is set to 1, RCR3 performs a comparison with the RYRCNT. From among 
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm 
register comparison is performed only on those with ENB bits set to 1, and if each of those 
coincides, an alarm flag of RCR1 is set to 1. 

0

1

2

3

4

5

6

7

Undefined

R/W

0

R

0

R

0

R

0

R

0

R

0

R

0

R

BIt:

Initial value:

R/W:

ENB

-

-

-

-

-

-

-

 

 

7 

ENB 

Undefined  R/W 

When this bit is set to 1, comparison of the year alarm 
register (RYRAR) and the year counter (RYRCNT) is 
performed. 

6 to 0 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value should 
always be 0.