Renesas R5S72621 User Manual
Section 15 Serial Communication Interface with FIFO
R01UH0134EJ0400 Rev. 4.00
Page 707 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Section 15 Serial Communication Interface with FIFO
This LSI has an eight-channel serial communication interface with FIFO that supports both
asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for
both transmission and reception independently for each channel that enable this LSI to perform
efficient high-speed continuous communication.
asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for
both transmission and reception independently for each channel that enable this LSI to perform
efficient high-speed continuous communication.
15.1
Features
Asynchronous serial communication:
Serial data communication is performed by start-stop in character units. This module can
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are eight selectable serial data
communication formats.
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are eight selectable serial data
communication formats.
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, framing, and overrun errors
Break detection: Break is detected when a framing error is followed by at least one frame
at the space 0 level (low level). It is also detected by reading the RxD level directly from
the serial port register when a framing error occurs.
at the space 0 level (low level). It is also detected by reading the RxD level directly from
the serial port register when a framing error occurs.
Clock synchronous serial communication: (SH7262: channels 0 to 2, SH7264: channels 0 to 3)
Serial data communication is synchronized with a clock signal. This module can
communicate with other chips having a clock synchronous communication function. There
is one serial data communication format.
communicate with other chips having a clock synchronous communication function. There
is one serial data communication format.
Data length: 8 bits
Receive error detection: Overrun errors
Full duplex communication: The transmitting and receiving sections are independent, so this
module can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering,
so high-speed continuous data transfer is possible in both the transmit and receive directions.
so high-speed continuous data transfer is possible in both the transmit and receive directions.
On-chip baud rate generator with selectable bit rates
Internal or external transmit/receive clock source: From either baud rate generator (internal) or
Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)