Renesas R5S72621 User Manual

Page of 2152
 
 
Section 15   Serial Communication Interface with FIFO 
 
 
Page 724 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
15.3.7
 
Serial Status Register (SCFSR) 
SCFSR is a 16-bit register. The upper 8 bits indicate the number of receive errors in the receive 
FIFO data register, and the lower 8 bits indicate the status flag indicating operating state. 
The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, 
TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read 
(after being set to 1). The PER flag (bits 15 to 12 and bit 2) and the FER flag (bits 11 to 8 and bit 
3) are read-only bits that cannot be written. 
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
R
R
R
R
R
R
R
R
R/(W)* R/(W)* R/(W)* R/(W)*
R
R
R/(W)* R/(W)*
Bit:
Initial value:
R/W:
Note:
Only 0 can be written to clear the flag after 1 is read.
*
PER[3:0]
FER[3:0]
ER
TEND
TDFE
BRK
FER
PER
RDF
DR
 
 
Bit Bit 
Name 
Initial 
Value R/W Description 
15 to 12  PER[3:0] 
0000 
Number of Parity Errors 
Indicate the quantity of data including a parity error in 
the receive data stored in the receive FIFO data 
register (SCFRDR). The value indicated by bits 15 to 
12 after the ER bit in SCFSR is set, represents the 
number of parity errors in SCFRDR. When parity 
errors have occurred in all 16-byte receive data in 
SCFRDR, PER[3:0] shows 0000. 
11 to 8 
FER[3:0] 
0000 
Number of Framing Errors 
Indicate the quantity of data including a framing error 
in the receive data stored in SCFRDR. The value 
indicated by bits 11 to 8 after the ER bit in SCFSR is 
set, represents the number of framing errors in 
SCFRDR. When framing errors have occurred in all 
16-byte receive data in SCFRDR, FER[3:0] shows 
0000.