Renesas R5S72621 User Manual

 

Section 15   Serial Communication Interface with FIFO 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 731 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

0 DR  0 R/(W)* Receive Data Ready 

Indicates that the quantity of data in the receive FIFO 
data register (SCFRDR) is less than the specified 
receive trigger number, and that the next data has not 
yet been received after the elapse of 15 ETU from the 
last stop bit in asynchronous mode. In clock 
synchronous mode, this bit is not set to 1. 

0: Receiving is in progress, or no receive data 

remains in SCFRDR after receiving ended normally

[Clearing conditions] 

  DR is cleared to 0 when the chip undergoes a 

power-on reset 

  DR is cleared to 0 when all receive data are read 

after 1 is read from DR and then 0 is written. 

  DR is cleared to 0 when all receive data are read 

after the direct memory access controller is 

activated by receive FIFO data full interrupt (RXI).

1: Next receive data has not been received 

[Setting condition] 

  DR is set to 1 when SCFRDR contains less data 

than the specified receive trigger number, and the 

next data has not yet been received after the 

elapse of 15 ETU from the last stop bit.*

1

 

Note:  1.  This is equivalent to 1.5 frames with the 8-

bit, 1-stop-bit format. (ETU: elementary 
time unit)  

Note:  *  Only 0 can be written to clear the flag after 1 is read.