Renesas R5S72621 User Manual

 

Section 15   Serial Communication Interface with FIFO 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 745 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can 
be cleared to 0 only if it has first been read (after being set to 1). 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R/(W)*

Bit:

Initial value:

R/W:

Note:

Only 0 can be written to clear the flag after 1 is read.

*

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

ORER

 

 

15 to 1 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

0 ORER 

0 R/(W)* Overrun Error 

Indicates the occurrence of an overrun error. 

0: Receiving is in progress or has ended normally*

1

 

[Clearing conditions] 

  ORER is cleared to 0 when the chip is a power-on 

reset 

  ORER is cleared to 0 when 0 is written after 1 is 

read from ORER. 

1: An overrun error has occurred*

2

 

[Setting condition] 

  ORER is set to 1 when the next serial receiving is 

finished while the receive FIFO is full of 16-byte 

receive data. 

Notes:  1.  Clearing the RE bit to 0 in SCSCR does 

not affect the ORER bit, which retains its 
previous value. 

 

2.  The receive FIFO data register 

(SCFRDR) retains the data before an 
overrun error has occurred, and the next 
received data is discarded. When the 
ORER bit is set to 1, the next serial 
reception cannot be continued.