Renesas R5S72621 User Manual
Section 15 Serial Communication Interface with FIFO
Page 774 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
15.6.7
Selection of Base Clock in Asynchronous Mode
In this LSI, when asynchronous mode is selected, the base clock frequency within a bit period can
be set to the frequency 16 or 8 times the bit rate by setting the ABCS bit in SCEMR.
be set to the frequency 16 or 8 times the bit rate by setting the ABCS bit in SCEMR.
Note that, however, if the base clock frequency 8 times the bit rate is used, receive margin is
decreased as calculated using equation 1 in section 15.6.6, Receive Data Sampling Timing and
Receive Margin (Asynchronous Mode).
decreased as calculated using equation 1 in section 15.6.6, Receive Data Sampling Timing and
Receive Margin (Asynchronous Mode).
If the desired bit rate can be set simply by setting SCBRR and the CKS1and CKS0 bits in
SCSMR, it is recommended to use the base clock frequency within a bit period 16 times the bit
rate (by setting the ABCS bit in SCEMR to 0). If an internal clock is selected as a clock source
and the SCK pin is not used, the bit rate can be increased without decreasing receive margin by
selecting double-speed mode for the baud rate generator (setting the BGDM bit in SCEMR to 1).
SCSMR, it is recommended to use the base clock frequency within a bit period 16 times the bit
rate (by setting the ABCS bit in SCEMR to 0). If an internal clock is selected as a clock source
and the SCK pin is not used, the bit rate can be increased without decreasing receive margin by
selecting double-speed mode for the baud rate generator (setting the BGDM bit in SCEMR to 1).