Renesas R5S72621 User Manual
Section 16 Renesas Serial Peripheral Interface
R01UH0134EJ0400 Rev. 4.00
Page 779 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
16.3
Register Descriptions
Table 16.2 shows the register configuration. These registers enable this module to perform the
following controls: specifying master/slave modes, specifying a transfer format, and controlling
the transmitter and receiver.
following controls: specifying master/slave modes, specifying a transfer format, and controlling
the transmitter and receiver.
Table 16.2 Register Configuration
Channel Register Name
Abbreviation*
1
R/W
Initial
Value
Value
Address
Access
Size
Size
0 Control
register_0
SPCR_0 R/W
H'00 H'FFFF8000
8,
16
Slave select polarity
register_0
register_0
SSLP_0 R/W
H'00 H'FFFF8001
8,
16
Pin control register_0 SPPCR_0
R/W
H'00 H'FFFF8002
8,
16
Status register_0 SPSR_0
R/(W)
*
2
H'60 H'FFFF8003
8,
16
Data register_0
SPDR_0
R/W Undefined
H'FFFF8004
8,16,32
Sequence control register_0 SPSCR_0 R/W
H'00 H'FFFF8008
8,
16
Sequence status register_0
SPSSR_0 R H'00 H'FFFF8009
8,
16
Bit rate register_0
SPBR_0
R/W H'FF
H'FFFF800A
8,
16
Data control register_0
SPDCR_0 R/W
H'20 H'FFFF800B
8,
16
Clock delay register_0
SPCKD_0
R/W H'00
H'FFFF800C
8,
16
Slave select negation delay
register_0
register_0
SSLND_0 R/W
H'00 H'FFFF800D
8,
16
Next-access delay
register_0
register_0
SPND_0 R/W
H'00 H'FFFF800E
8
Command register_00
SPCMD_00 R/W H'070D H'FFFF8010
16
Command register_01
SPCMD_01 R/W H'070D H'FFFF8012
16
Command register_02
SPCMD_02 R/W H'070D H'FFFF8014
16
Command register_03
SPCMD_03 R/W H'070D H'FFFF8016
16
Buffer control register_0
SPBFCR_0 R/W H’00
H'FFFF8020
8,
16
Buffer data count setting
register_0
register_0
SPBFDR_0 R
H'0000 H'FFFF8022
16