Renesas R5S72621 User Manual
Section 17 I
2
C Bus Interface 3
Page 862 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
17.3.5
I
2
C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
TDRE
TEND
RDRF NACKF STOP AL/OVE
AAS
ADZ
Bit Bit
Name
Initial
Value
Value
R/W Description
7
TDRE
0
R/W
Transmit Data Register Empty
[Clearing conditions]
When 0 is written in TDRE after reading TDRE = 1
When data is written to ICDRT
[Setting conditions]
When data is written to ICDRT
[Setting conditions]
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
When TRS is set
When the start condition (including retransmission)
When the start condition (including retransmission)
is issued
When slave mode is changed from receive mode to
transmit mode
6 TEND
0 R/W
Transmit
End
[Clearing conditions]
When 0 is written in TEND after reading TEND = 1
When data is written to ICDRT
[Setting conditions]
When data is written to ICDRT
[Setting conditions]
When the ninth clock of SCL rises with the I
2
C bus
format while the TDRE flag is 1
When the final bit of transmit frame is sent with the
clocked synchronous serial format