Renesas R5S72621 User Manual
Section 17 I
2
C Bus Interface 3
Page 886 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
17.5
Interrupt Requests
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK detection, STOP recognition, and arbitration lost/overrun error. Table 17.4 shows the
contents of each interrupt request.
NACK detection, STOP recognition, and arbitration lost/overrun error. Table 17.4 shows the
contents of each interrupt request.
Table 17.4 Interrupt Requests
Interrupt Request
Abbreviation
Interrupt Condition
I
2
C Bus
Format
Clocked Synchronous
Serial Format
Serial Format
Transmit data Empty
TXI
(TDRE = 1) (TIE = 1)
Transmit end
TEI
(TEND = 1) (TEIE = 1)
Receive data full
RXI
(RDRF = 1) (RIE = 1)
STOP recognition
STPI
(STOP = 1) (STIE = 1)
NACK detection
NAKI
{(NACKF = 1) + (AL = 1)}
(NAKIE = 1)
(NAKIE = 1)
Arbitration lost/
overrun error
overrun error
When the interrupt condition described in table 17.4 is 1, the CPU executes an interrupt exception
handling. Note that a TXI or RXI interrupt can activate the direct memory access controller if the
setting for direct memory access controller activation has been made. In such a case, an interrupt
request is not sent to the CPU. Interrupt sources should be cleared in the exception handling. The
TDRE and TEND bits are automatically cleared to 0 by writing the transmit data to ICDRT. The
RDRF bit is automatically cleared to 0 by reading ICDRR. The TDRE bit is set to 1 again at the
same time when the transmit data is written to ICDRT. Therefore, when the TDRE bit is cleared to
0, then an excessive data of one byte may be transmitted.
handling. Note that a TXI or RXI interrupt can activate the direct memory access controller if the
setting for direct memory access controller activation has been made. In such a case, an interrupt
request is not sent to the CPU. Interrupt sources should be cleared in the exception handling. The
TDRE and TEND bits are automatically cleared to 0 by writing the transmit data to ICDRT. The
RDRF bit is automatically cleared to 0 by reading ICDRR. The TDRE bit is set to 1 again at the
same time when the transmit data is written to ICDRT. Therefore, when the TDRE bit is cleared to
0, then an excessive data of one byte may be transmitted.