Renesas R5S72621 User Manual

 
Section 17   I

2

C Bus Interface 3 

Page 890 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

In multi-master operation, when the transfer rate setting for this module (ICCR1.CKS[3:0]) makes 
this LSI slower than the other masters, pulse cycles with an unexpected length will infrequently be 
output on SCL. 

Be sure to specify a transfer rate that is at least 1/1.8 of the fastest transfer rate among the other 
masters. 

Reading ICDRR around the falling edge of the 8th clock might fail to fetch the receive data. 

In addition, when RCVD is set to 1 around the falling edge of the 8th clock and the receive buffer 
full, a stop condition may not be issued. 

Use either 1 or 2 below as a measure against the situations above. 

1.  In master receive mode, read ICDRR before the rising edge of the 8th clock. 

2.  In master receive mode, set the RCVD bit to 1 so that transfer proceeds in byte units. 
 

In master receive mode operation, set ACKBT before the falling edge of the 8th SCL cycle of the 
last data being continuously transferred. Not doing so can lead to an overrun for the slave 
transmission device.