Renesas R5S72621 User Manual

 

 

Section 18   Serial Sound Interface 

 

 

Page 898 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

2 

Control register 2 

SSICR_2 

R/W H'00000000

H'FFFF1000  8, 16, 32 

 Status 

register 

2 

SSISR_2 

R/W*

1

 H'02000013

H'FFFF1004  8, 16, 32 

 FIFO 

control 

register 2 

SSIFCR_2 R/W 

H'00000000

H'FFFF1010  8, 16, 32 

 

FIFO status register 
2 

SSIFSR_2 R/(W)*

2

H'00010000

H'FFFF1014  8, 16, 32 

 Transmit 

FIFO 

data 

register 2 

SSIFTDR_2 W 

Undefined 

H'FFFF1018 

32 

 Receive 

FIFO 

data 

register 2 

SSIFRDR_2 R 

Undefined H'FFFF101C 

32 

3 

Control register 3 

SSICR_3 

R/W H'00000000

H'FFFF1800  8, 16, 32 

 Status 

register 

3 

SSISR_3 

R/W*

1

 H'02000013

H'FFFF1804  8, 16, 32 

 FIFO 

control 

register 3 

SSIFCR_3 R/W 

H'00000000

H'FFFF1810  8, 16, 32 

 

FIFO status register 
3 

SSIFSR_3 R/(W)*

2

H'00010000

H'FFFF1814  8, 16, 32 

 Transmit 

FIFO 

data 

register 3 

SSIFTDR_3 W 

Undefined 

H'FFFF1818 

32 

 Receive 

FIFO 

data 

register 3 

SSIFRDR_3 R 

Undefined H'FFFF181C 

32 

Notes: 1. Although bits 29 to 26 in these registers can be read from or written to, bits other than 

these are read-only. For details, refer to section 18.3.2, Status Register (SSISR). 

 2. 

To 

bits 16 and 0 in these registers, only 0 can be written to clear the flags. Other bits 

are read-only. For details, refer to section 18.3.6, FIFO Status Register (SSIFSR).