Renesas R5S72621 User Manual

 

Section 19   Serial I/O with FIFO 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 939 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

Section 19   Serial I/O with FIFO 

This LSI includes a clock-synchronized serial I/O module with FIFO. 

  Serial transfer 

 

16-stage 32-bit FIFOs (independent transmission and reception) 

 

Supports 8-bit monaural/16-bit monaural/16-bit stereo audio input and output 

 

MSB first for data transmission 

 

Supports a maximum of 48-kHz sampling rate 

 

Synchronization by frame synchronization pulse 

 

Connectable to linear, audio, or A-Law or 

-Law CODEC chip 

 

Supports both master and slave modes 

  Serial clock 

 

AUDIO_CLK or AUDIO_X1 can be selected as the clock source. 

  Interrupts: One type 
  DMA transfer: Two types 

 

Transmit FIFO transfer requests and receive FIFO transfer requests