Renesas R5S72621 User Manual
Section 19 Serial I/O with FIFO
Page 950 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
19.3.5
Status Register (SISTR)
SISTR shows the state of this module. Each bit in this register becomes an interrupt source for this
module when the corresponding bit in SIIER is set to 1.
module when the corresponding bit in SIIER is set to 1.
SISTR is initialized in module stop mode.
Bit:
Initial Value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
-
-
TFEMP TDREQ
-
-
RFFUL RDREQ
-
-
-
FSERR TFOVF TFUDF RFUDF RFOVF
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
15
0 R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.
14
0 R
Reserved
The read value is undefined. The write value should
always be 0.
always be 0.
13 TFEMP
0
R Transmit
FIFO
Empty
0: Indicates that transmit FIFO is not empty
1: Indicates that transmit FIFO is empty
This bit is valid when the TXE bit in SICTR is 1.
If SITDR is written, this module clears this bit.
Note: When this bit is set to 1, a transmit FIFO
If SITDR is written, this module clears this bit.
Note: When this bit is set to 1, a transmit FIFO
underflow may have occurred. Do not use this bit
at the timing of writing to the transmit data
register.
at the timing of writing to the transmit data
register.