Renesas R5S72621 User Manual

 

 

Section 19   Serial I/O with FIFO 

 

 

Page 958 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

7 

6 

5 

RFWM2 

RFWM1 

RFWM0 

0 

0 

0 

R/W 

R/W 

R/W 

Receive FIFO Watermark 

000: Issue a transfer request when 1 stage or more of the 

receive FIFO are valid. 

001: Setting prohibited 

010: Setting prohibited 

011: Setting prohibited 

100: Issue a transfer request when 4 or more stages of 

the receive FIFO are valid. 

101: Issue a transfer request when 8 or more stages of 

the receive FIFO are valid. 

110: Issue a transfer request when 12 or more stages of 

the receive FIFO are valid. 

111: Issue a transfer request when 16 stages of the 

receive FIFO are valid. 

  A transfer request to the receive FIFO is issued by the 

RDREQE bit in SISTR.  

  The receive FIFO is always used as 16 stages of the 

FIFO regardless of these bit settings.  

4 

3 

2 

1 

0 

RFUA4 

RFUA3 

RFUA2 

RFUA1 

RFUA0 

0 

0 

0 

0 

0 

R 

R 

R 

R 

R 

Receive FIFO Usable Area 

Indicate the number of stages of FIFO that can be 
transferred as B'00000 (empty) to B'10000 (full).