Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
194
Datasheet
7.1.1
ID—Identifiers
B/D/F/Type:
0/3/0/PCI
Address Offset: 0–3h
Default Value:
29F48086h
Access:
RO
Size:
32 bits
7.1.2
CMD—Command
B/D/F/Type:
0/3/0/PCI
Address Offset: 4–5h
Default Value:
0000h
Access:
RO, RW
Size:
16 bits
Bit
Access
Default
Value
Description
31:16
RO
29F4h
Device ID (DID): Device ID (DID): This field indicates what device number
assigned by Intel.
assigned by Intel.
15:0
RO
8086h
Vendor ID (VID): Vendor ID (VID): This field indicates Intel is the vendor,
assigned by the PCI SIG.
assigned by the PCI SIG.
Bit
Access
Default
Value
Description
15:11
RO
00000b Reserved
10
RW
0b
Interrupt Disable (ID): Disables this device from generating PCI line based
interrupts. This bit does not have any effect on MSI operation.
interrupts. This bit does not have any effect on MSI operation.
9:3
RO
00h
Reserved
2
RW
0b
Bus Master Enable (BME): Controls the HECI host controller's ability to act as
a system memory master for data transfers. When this bit is cleared, HECI bus
master activity stops and any active DMA engines return to an idle condition.
This bit is made visible to firmware through the H_PCI_CSR register, and
changes to this bit may be configured by the H_PCI_CSR register to generate an
ME MSI.
0 = HECI is blocked from generating MSI to the host processor.
Note that this bit does not block HECI accesses to ME-UMA, i.e. writes or reads
to the host and ME circular buffers through the read window and write window
registers still cause ME backbone transactions to ME-UMA.
a system memory master for data transfers. When this bit is cleared, HECI bus
master activity stops and any active DMA engines return to an idle condition.
This bit is made visible to firmware through the H_PCI_CSR register, and
changes to this bit may be configured by the H_PCI_CSR register to generate an
ME MSI.
0 = HECI is blocked from generating MSI to the host processor.
Note that this bit does not block HECI accesses to ME-UMA, i.e. writes or reads
to the host and ME circular buffers through the read window and write window
registers still cause ME backbone transactions to ME-UMA.
1
RW
0b
Memory Space Enable (MSE): Controls access to the HECI host controller’s
memory mapped register space.
memory mapped register space.
0
RO
0b
Reserved