Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
Datasheet
77
DRAM Controller Registers (D0:F0)
5.1.16
DMIBAR—Root Complex Register Range Base Address
B/D/F/Type:
0/0/0/PCI
Address Offset: 68–6Fh
Default Value:
0000000000000000h
Access:
RO, RW/L
Size:
64 bits
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the MCH. There is no physical memory within this 4 KB window that can
be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3
compliant memory mapped space. On reset, the Root Complex configuration space is
disabled and must be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0]. All
the Bits in this register are locked in Intel TXT mode.
Bit
Access
Default
Value
Description
63:36
RO
0000000h
Reserved
35:12
RW/L
000000h
DMI Base Address (DMIBAR): This field corresponds to bits 35:12 of the
base address DMI configuration space. BIOS will program this register
resulting in a base address for a 4 KB block of contiguous memory address
space. This register ensures that a naturally aligned 4KB space is allocated
within the first 64 GB of addressable memory space. System Software uses
this base address to program the DMI register set. All the Bits in this register
are locked in Intel TXT mode.
base address DMI configuration space. BIOS will program this register
resulting in a base address for a 4 KB block of contiguous memory address
space. This register ensures that a naturally aligned 4KB space is allocated
within the first 64 GB of addressable memory space. System Software uses
this base address to program the DMI register set. All the Bits in this register
are locked in Intel TXT mode.
11:1
RO
000h
Reserved
0
RW/L
0b
DMIBAR Enable (DMIBAREN):
0 = DMIBAR is disabled and does not claim any memory
1 = DMIBAR memory mapped accesses are claimed and decoded
0 = DMIBAR is disabled and does not claim any memory
1 = DMIBAR memory mapped accesses are claimed and decoded
appropriately
This register is locked by Intel TXT.