Renesas SH7262 R5S72620 User Manual
Section 26 USB 2.0 Host/Function Module
Page 1374 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
13
DCLRM
0
R/W
Auto Buffer Memory Clear Mode Accessed after
Specified Pipe Data is Read
Specified Pipe Data is Read
Enables or disables the buffer memory to be cleared
automatically after data has been read out using the
selected pipe.
automatically after data has been read out using the
selected pipe.
0: Auto buffer clear mode is disabled.
1: Auto buffer clear mode is enabled.
With this bit set to 1, this module sets BCLR to 1 for
the FIFO buffer of the selected pipe on receiving a
zero-length packet while the FIFO buffer assigned to
the selected pipe is empty, or on receiving a short
packet and reading the data while BFRE is 1.
the FIFO buffer of the selected pipe on receiving a
zero-length packet while the FIFO buffer assigned to
the selected pipe is empty, or on receiving a short
packet and reading the data while BFRE is 1.
When using this module with the BRDYM bit set to 1,
set this bit to 0.
set this bit to 0.
12
DREQE
0
R/W
DMA Transfer Request Enable
Enables or disables the DMA transfer request to be
issued.
issued.
0: Request disabled
1: Request enabled
Before setting this bit to 1 to enable the DMA transfer
request to be issued, set the CURPIPE bits.
request to be issued, set the CURPIPE bits.
Before modifying the CURPIPE bit setting, set this bit
to 0.
to 0.