Renesas SH7262 R5S72620 User Manual
Section 26 USB 2.0 Host/Function Module
Page 1522 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
When CURPIPE setting is DCP (000) for CFIFO
Start
Set ISEL to 1.
MBW modification end
[1]
[2]
Read ISEL to check that
the read value agrees with
the written value.
the read value agrees with
the written value.
Read ISEL to check that
the read value agrees with
the written value.
the read value agrees with
the written value.
Set MBW and ISEL
simultaneously.
simultaneously.
[1]
[2]
Select the writing direction.
Set MBW to any value and
set ISEL to select the reading
direction.
set ISEL to select the reading
direction.
Figure 26.15 MBW Modification Procedure Example When CURPIPE Setting is DCP (000)
(3) DMA Transfers (D0FIFO/D1FIFO Port)
(a) Overview of DMA Transfers
For pipes 1 to 9, the FIFO port can be accessed using the direct memory access controller. When
accessing the buffer for the pipe targeted for DMA transfer is enabled, a DMA transfer request is
issued.
accessing the buffer for the pipe targeted for DMA transfer is enabled, a DMA transfer request is
issued.
The unit of transfer to the FIFO port should be selected using the MBW bit in DnFIFOSEL and
the pipe targeted for the DMA transfer should be selected using the CURPIPE bit. The selected
pipe should not be changed during the DMA transfer.
the pipe targeted for the DMA transfer should be selected using the CURPIPE bit. The selected
pipe should not be changed during the DMA transfer.
(b) Auto Recognition of DMA Transfer Completion
With this module, it is possible to complete FIFO data writing through DMA transfer by
controlling DMA transfer end signal input. The DMA transfer end signal is output from the direct
memory access controller when the controller transfers data through DMA for the times specified
by the DMA transfer count register (DMATCR) of the direct memory access controller. When a
transfer end signal is sampled, the module enables buffer memory transmission (the same
controlling DMA transfer end signal input. The DMA transfer end signal is output from the direct
memory access controller when the controller transfers data through DMA for the times specified
by the DMA transfer count register (DMATCR) of the direct memory access controller. When a
transfer end signal is sampled, the module enables buffer memory transmission (the same