Renesas SH7262 R5S72620 User Manual

 
Section 9   Bus State Controller 
 

Page 358 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

[4] WM 

in 

CSnWCR 

This bit enables or disables external 

WAIT pin input for the memory 
types other than SDRAM. When 
this bit is cleared to 0 (external 

WAIT enabled), one idle cycle is 
inserted to check the external 

WAIT 

pin input after the access is 
completed. When this bit is set to 1 
(disabled), no idle cycle is 
generated. 

0 or 1 

 

[5] Read 

data 

transfer cycle 

One idle cycle is inserted after a 
read access is completed. This idle 
cycle is not generated for the first or 
middle cycles in divided access 
cycles. This is neither generated 
when the HW[1:0] bits in CSnWCR 
are not B'00. 

0 or 1 

One idle cycle is always 
generated after a read cycle 
with SDRAM or PCMCIA 
interface. 

[6] Internal 

bus 

idle cycles, etc.

External bus access requests from 
the CPU or the direct memory 
access controller and their results 
are passed through the internal 
bus. The external bus enters idle 
state during internal bus idle cycles 
or while a bus other than the 
external bus is being accessed. 
This condition is not effective for 
divided access cycles, which are 
generated by the bus state 
controller when the access size is 
larger than the external data bus 
width. 

0 or 
larger 

The number of internal bus 
idle cycles may not become 
0 depending on the I

:B 

clock ratio. Tables 9.17 and 
9.18 show the relationship 
between the clock ratio and 
the minimum number of 
internal bus idle cycles.