Renesas R5S72643 User Manual
Section 24 A/D Converter
R01UH0134EJ0400 Rev. 4.00
Page 1269 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Typical operations when a single channel (AN1) is selected in single mode are described next.
Figure 24.2 shows a timing diagram for this example (the bits which are set in this example belong
to ADCSR).
Figure 24.2 shows a timing diagram for this example (the bits which are set in this example belong
to ADCSR).
1. Single mode is selected, input channel AN1 is selected (CH[2:0] = 001), the A/D interrupt is
enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
2. When A/D conversion is completed, the A/D conversion result is transferred into ADDRB. At
the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter
becomes idle.
becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The routine reads ADF = 1, and then writes 0 to the ADF flag.
6. The routine reads and processes the A/D conversion result (ADDRB).
7. Execution of the A/D interrupts handling routine ends. Then, when the ADST bit is set to 1,
A/D conversion starts and steps 2 to 7 are executed.