Renesas R5S72643 User Manual
Section 25 NAND Flash Memory Controller
R01UH0134EJ0400 Rev. 4.00
Page 1329 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(1) Sector Address
Figure 25.11 shows the relationship between the physical sector address of NAND-type flash
memory and the address of flash memory.
memory and the address of flash memory.
Row2
Row3
Row1
Col1
0
0
0
0
0
0
Col2
0
0
0
0
0
0
Order of address output to NAND-type flash memory I/O
Col
Col2
Row1
Row2
Order of address output to NAND-type flash memory I/O
Col
Col2
Row1
Row2
Row3
When ADRCNT2 = 1 (Bits[25:18] are valid.)
FLADR[1:0] specify the boundary
address for column address in the
unit of 512 + 16 bytes.
When NAND-type flash memory
(2048 + 64 bytes) is used, set
FLADR[1:0] as follows.
00: 0 byte
01: 512 + 16 bytes
10: 1024 + 32 bytes
11: 1536 + 48 bytes
address for column address in the
unit of 512 + 16 bytes.
When NAND-type flash memory
(2048 + 64 bytes) is used, set
FLADR[1:0] as follows.
00: 0 byte
01: 512 + 16 bytes
10: 1024 + 32 bytes
11: 1536 + 48 bytes
Note:
Bit 25
Bit 0
NAND-type flash memory (2048 + 64 bytes)
Physical sector address
Bit 25
Bit 0
Physical sector address bit (FLADR[25:0])
Row3
Row2
Row1
Col
[Legend]
Col: Column address
Row: Row address (page address)
Row: Row address (page address)
When ADRCNT2 = 0
When FADRCNT2 = 1, FLADR[25:18] are valid.
Set the invalid bit to 0 depending on the capacity of flash memory.
Set the invalid bit to 0 depending on the capacity of flash memory.
Note:
Figure 25.11 Relationship between Sector Number and Address Expansion of
NAND-Type Flash Memory