Renesas R5S72643 User Manual
Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00
Page 1475 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(5) Register Access Wait Control
There is a restriction on the cycle time for accessing the registers of this module except for
SYSSTS as given below.
SYSSTS as given below.
Wait-related restriction: The cycle time for successive accesses to the USB 2.0 host/function
module must be a duration of at least four USB clock (48 MHz) cycles (83.33 ns). To fulfill the
above restriction, a register access wait control is necessary using the BWAIT[3:0] bits in
BUSWAIT. The initial value is the maximum value (access cycles = 17 clock cycles). The
optimum value should be found and set.
module must be a duration of at least four USB clock (48 MHz) cycles (83.33 ns). To fulfill the
above restriction, a register access wait control is necessary using the BWAIT[3:0] bits in
BUSWAIT. The initial value is the maximum value (access cycles = 17 clock cycles). The
optimum value should be found and set.
Setting example 1: When successively accessing the registers of this module
Bus clock frequency: 72 MHz
Calculation: (2 cycles (access cycles for the registers of this module) + 1 cycle (interval between
successive accesses) + BWAIT)
successive accesses) + BWAIT)
1/72 MHz 83.33 ns
BWAIT = 3
Setting example 2: When sending data from the on-chip high-speed RAM to the FIFO port register
through DMA transfer
through DMA transfer
Bus clock frequency: 72 MHz
Calculation: (2 cycles (access cycles for the registers of this module) + 2 cycles (access cycles for
the on-chip high-speed RAM) + BWAIT)
the on-chip high-speed RAM) + BWAIT)
1/72 MHz 83.33 ns
BWAIT = 2