Renesas R5S72643 User Manual
Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00
Page 1507 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(7) Data PID Sequence Bit
This module automatically toggles the sequence bit in the data PID when data is transferred
normally in the control transfer data stage, bulk transfer and interrupt transfer. The sequence bit of
the data PID that was transmitted can be confirmed with the SQMON bit in DCPCTR and
PIPEnCTR. When data is transmitted, the sequence bit switches at the timing at which the ACK
handshake is received. When data is received, the sequence bit switches at the timing at which the
ACK handshake is transmitted. The SQCLR bit in DCPCTR and the SQSET bit in PIPEnCTR can
be used to change the data PID sequence bit.
normally in the control transfer data stage, bulk transfer and interrupt transfer. The sequence bit of
the data PID that was transmitted can be confirmed with the SQMON bit in DCPCTR and
PIPEnCTR. When data is transmitted, the sequence bit switches at the timing at which the ACK
handshake is received. When data is received, the sequence bit switches at the timing at which the
ACK handshake is transmitted. The SQCLR bit in DCPCTR and the SQSET bit in PIPEnCTR can
be used to change the data PID sequence bit.
When the function controller function has been selected and control transfer is used, this module
automatically sets the sequence bit when a stage transition is made. The bit is set to DATA1 when
the setup stage ends. In the status stage, DATA1 is returned without referencing the sequence bit.
Therefore, settings are not required. However, when the host controller function has been selected
and control transfer is used, the sequence bit should be set at the stage transition.
automatically sets the sequence bit when a stage transition is made. The bit is set to DATA1 when
the setup stage ends. In the status stage, DATA1 is returned without referencing the sequence bit.
Therefore, settings are not required. However, when the host controller function has been selected
and control transfer is used, the sequence bit should be set at the stage transition.
For the Clearfeature request transmission or reception, the data PID sequence bit should be set,
regardless of whether the host controller function or function controller function is selected.
regardless of whether the host controller function or function controller function is selected.
With pipes for which isochronous transfer has been set, sequence bit operation cannot be carried
out using the SQSET bit.
out using the SQSET bit.
(8) Response PID = NAK Function
This module has a function that disables pipe operation (PID response = NAK) at the timing at
which the final data packet of a transaction is received (this module automatically distinguishes
this based on reception of a short packet or the transaction counter) by setting the SHTNAK bit in
PIPECFG to 1.
which the final data packet of a transaction is received (this module automatically distinguishes
this based on reception of a short packet or the transaction counter) by setting the SHTNAK bit in
PIPECFG to 1.
When a double buffer is being used for the buffer memory, using this function enables reception
of data packets in transfer units. If pipe operation has disabled, the pipe has to be set to the enabled
state again (PID response = BUF).
of data packets in transfer units. If pipe operation has disabled, the pipe has to be set to the enabled
state again (PID response = BUF).
This function can be used only when bulk transfers are used.