Renesas R5S72643 User Manual
Section 27 Video Display Controller 3
Page 1578 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
1 HSYNC_TIM
0
R/W
Specifies
the timing of the DV_HSYNC input
signal.
0: Latched at the rising edge of the DV_CLK.
1: Latched at the falling edge of the DV_CLK.
0
VIDEO_TIM
0
R/W
Specifies the timing of the DV_DATA input signal.
0: Latched at the rising edge of the DV_CLK.
1: Latched at the falling edge of the DV_CLK.