Renesas R5S72643 User Manual
Section 27 Video Display Controller 3
Page 1630 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(1) Video Display Position and Register Settings
As the display block does not have frame memory, specify through registers the vertical start
position and number of line buffers for the video according to the panel specifications (HSYNC
cycle). For the vertical video position, first calculate the register settings to place the video along
the top end, and then calculate the settings to place the video at the center or along the bottom end.
position and number of line buffers for the video according to the panel specifications (HSYNC
cycle). For the vertical video position, first calculate the register settings to place the video along
the top end, and then calculate the settings to place the video at the center or along the bottom end.
(a) Register settings for vertical position
Step 1: Calculate the settings to place the video along the top end.
Table 27.20 List of Parameters (registers are shaded in grey)
Register Name or Value
Unit
(1)
T (Hsync_in): HSYNC cycle of the input video 0.064
ms
(2)
Vertical size of the valid video
VIDEO_SIZE[24:16] Line
(3)
T (Hsync_out): HSYNC cycle for the panel
Depends on the panel specifications
ms
(4) Vertical size of the video to be displayed
VIDEO_DISP_SIZE[24:16] Line
(5)
Line buffer margin
6 or a greater value
Line
(6)
Vertical start position of the valid video in the
TOP field
TOP field
VIDEO_VSTART[24:16] Line
(7)
Vertical start position of the valid video in the
BOTTOM field
BOTTOM field
VIDEO_VSTART[8:0] Line
(8)
Number of lines between the reference Vsync
and the displayable area
and the displayable area
Depends on the panel specifications
Line