Renesas R5S72643 User Manual

 
Section 28   Sampling Rate Converter 

Page 1660 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

1.  Assign IDEI of this module to one channel of the direct memory access controller. 

2.  Set the IEN bit in SRCIDCTRL to 1. 

3.  When the IINT bit in SRCSTAT is set to 1, the IDE interrupt request is issued thus activating 

the direct memory access controller. When the direct memory access controller has written 
data to the SRCID thus resulting in the number of data units in the input data FIFO exceeding 
that of the triggering number specified by the IFTRG1 and IFTRG 0 bits in SRCIDCTRL, the 
IINT bit is cleared to 0. 

4.  Repeat step 3 until all the data has been input, and write 1 to the FL bit in SRCCTRL. 
 
(3)  When Serial Sound Interface Interrupts are Used for Activating Direct Memory Access 

1.  Assign the serial sound interface to one channel of the direct memory access controller as a 

DMA transfer request source. Set SSIFRDR of the serial sound interface as a transfer source 
and SRCID of the sampling rate converter as a transfer destination, and set the serial source 
interface to enable reception operation. 

2.  When the RDF bit in SSIFSR is set to 1, the serial sound interface interrupt request is issued 

thus activating the direct memory access controller. The direct memory access controller then 
reads data from SSIFRDR and writes the data to SRCID. 

3.  Repeat step 2 until all the data has been input, and write 1 to the FL bit in SRCCTRL.