Renesas R5S72643 User Manual
Page 2068 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
Item Page
Revision
(See Manual for Details)
9.5.11 Wait between
Access Cycles
Access Cycles
Table 9.19 Number of Idle
Cycles Inserted between
Access Cycles to Different
Memory Types
Cycles Inserted between
Access Cycles to Different
Memory Types
362
Table amended and note added
e
l
c
y
C
t
x
e
N
Previous Cycle SRAM
Burst ROM
(Asynchronous)
MPX-
I/O
Byte
SRAM
(BAS = 0)
Byte
SRAM
(BAS = 1) SDRAM
SDRAM
(Low-
Frequency
Mode)
PCMCIA
Burst ROM
(Synchronous)
SRAM 0
0
1
0 0/1*
1
0/1*
1
1.5
0
0
Burst ROM
(asynchronous)
0 0
1
0
0/1*
1
0/1*
1
1.5
0
0
MPX-I/O 1
1
0
1 1 1 1.5 1 1
Byte SRAM
(BAS = 0)
0 0
1
0
0/1*
1
0/1*
1
1.5
0
0
Byte SRAM
(BAS = 1)
0/1*
1
0/1*
1
1/2*
1
0/1*
1
0
0 1.5
0/1*
1
0/1*
1
SDRAM 1
1
2
1 0 0
⎯ 1 1
SDRAM
(low-frequency
mode)
1.5 1.5
2.5
1.5
0.5
⎯ 1
1.5 1.5
PCMCIA 0
0
1
0 0/1*
2
0/1*
2
1.5
0
0
Burst ROM
(synchronous)
0 0
1
0
1 1 1.5 0 0
Notes: 1. The number of idle cycles is determined by the setting of the CSnWCR.HW[1:0] bits on
the previous cycle. The number of idle cycles will be the number shown at the left when
HW[1:0]
HW[1:0]
≠ B'00, will be the number shown at the right when HW[1:0] = B'00. Also, for
CSn spaces for which the CSnWCR.HW[1:0] bits do not exist, the number of idle cycles
shown at the right will be used.
shown at the right will be used.
2.
The
number of idle cycles is determined by the setting of the CSnWCR.TEH[3:0] bits on
the previous cycle. The number of idle cycles will be the number shown at the left when
TEH[3:0]
TEH[3:0]
≠ B'0000, will be the number shown at the right when TEH[3:0] = B'0000.
9.5.13 Others
(3) On-Chip Peripheral
Module Access
Module Access
368 Description
amended
For example, a case is described here in which the system
is transferring to the software standby mode for power
savings. To make this transition, the SLEEP instruction
must be performed after setting the STBY bit in the
STBCR1 register to 1. However a dummy read of the
STBCR1 register is required before executing the SLEEP
instruction. If a dummy read is omitted, the CPU executes
the SLEEP instruction before the STBY bit is set to 1, thus
the system enters sleep mode not software standby mode.
A dummy read of the STBCR1 register is indispensable to
complete writing to the STBY bit.
is transferring to the software standby mode for power
savings. To make this transition, the SLEEP instruction
must be performed after setting the STBY bit in the
STBCR1 register to 1. However a dummy read of the
STBCR1 register is required before executing the SLEEP
instruction. If a dummy read is omitted, the CPU executes
the SLEEP instruction before the STBY bit is set to 1, thus
the system enters sleep mode not software standby mode.
A dummy read of the STBCR1 register is indispensable to
complete writing to the STBY bit.
10.4.4 DMA Transfer Types
Table 10.8 Supported DMA
Transfers
Transfers
417 Table
amended
n
o
i
t
a
n
i
t
s
e
D
r
e
f
s
n
a
r
T
Transfer Source
External
Device with
DACK
Device with
DACK
External
Memory
Memory
Memory-
Mapped
External Device
Mapped
External Device
On-Chip
Peripheral
Module
Peripheral
Module
On-Chip
Memory
Memory
External device
with DACK
with DACK
Not available Dual, single Dual, single
Dual Dual
External memory Dual, single
Dual Dual Dual Dual
Memory-mapped
external device
external device
Dual, single
Dual Dual Dual Dual
On-chip
peripheral
module
peripheral
module
Dual Dual Dual Dual Dual
On-chip memory Dual Dual Dual Dual Dual