Renesas R5S72643 User Manual
Section 8 Cache
Page 216 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Table 8.3
Way to be Replaced when a Cache Miss Occurs in PREF Instruction
LE W3LOAD* W3LOCK W2LOAD*
W2LOCK
Way to be Replaced
0 x
x
x
x
Decided by LRU (table 8.1)
1 x
0 x
0
Decided by LRU (table 8.1)
1 x
0
0
1
Decided by LRU (table 8.5)
1
0 1 x
0
Decided by LRU (table 8.6)
1
0 1 0 1 Decided
by
LRU
(table
8.7)
1 0
x
1 1 Way
2
1
1 1 0 x
Way 3
[Legend]
x: Don't
care
Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time.
Table 8.4
Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction
LE W3LOAD* W3LOCK W2LOAD*
W2LOCK
Way to be Replaced
0 x
x
x x
Decided by LRU (table 8.1)
1
x
0
x
0
Decided by LRU (table 8.1)
1
x
0
x
1
Decided by LRU (table 8.5)
1
x
1
x
0
Decided by LRU (table 8.6)
1
x
1
x
1
Decided by LRU (table 8.7)
[Legend]
x: Don't
care
Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time.
Table 8.5
LRU and Way Replacement (when W2LOCK=1 and W3LOCK=0)
LRU (Bits 5 to 0)
Way to be Replaced
000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100
3
000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111
1
101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111
0