Renesas R5S72643 User Manual

 

 

 

 

 

Section 9   Bus State Controller 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 241 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

5 

DMAIWA 

0 

R/W 

Method of inserting wait states between access 
cycles when DMA single address transfer is 
performed. 

Specifies the method of inserting the idle cycles 
specified by the DMAIW[2:0] bit. Clearing this bit will 
make this LSI insert the idle cycles when another 
device, which includes this LSI, drives the data bus 
after an external device with DACK drove it. However, 
when the external device with DACK drives the data 
bus continuously, idle cycles are not inserted. Setting 
this bit will make this LSI insert the idle cycles after an 
access to an external device with DACK, even when 
the continuous access cycles to an external device 
with DACK are performed. 

0: Idle cycles inserted when another device drives the 

data bus after an external device with DACK drove 
it. 

1: Idle cycles always inserted after an access to an 

external device with DACK 

4 

 1 

R 

Reserved 

This bit is always read as 1. The write value should 
always be 1. 

3, 2 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

1 

HIZMEM 

0 

R/W 

High-Z Memory Control 

Specifies the pin state in software standby mode or 
deep standby mode for A25 to A0, 

BS, CSn, CS2x, 

RD/

WR, WEn/DQMx/AH, and RD. At bus-released 

state, these pin are high-impedance states regardless 
of the setting value of the HIZMEM bit. 

0: High impedance in software standby mode or deep 

standby mode. 

1: Driven in software standby mode or deep standby 

mode