Renesas R5S72643 User Manual

 

Section 15   Serial Communication Interface with FIFO 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 709 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

Figure 15.1 shows a block diagram. Note that some channels do not have SCK, 

CTS and RTS 

pins. 

P

φ

SCFRDR (16 stages)

SCFTDR (16 stages)

SCRSR

SCTSR

SCSMR

SCLSR

SCFDR

SCFCR

SCFSR

SCSCR

SCSPTR

SCBRR

TXI
RXI
ERI

BRI

P

φ/4

P

φ/16

P

φ/64

RTS

CTS

SCK

TxD

RxD

 

Serial communication interface with FIFO  

Module data bus

Parity generation

Parity check

Transmission/reception

control

Baud rate
generator

Clock

External clock

Bus interface

Peripheral
bus

SCRSR:
SCFRDR:
SCTSR:
SCFTDR:
SCSMR:
SCSCR:
SCEMR:

[Legend]

SCFSR:
SCBRR:
SCSPTR:
SCFCR:
SCFDR:
SCLSR:

Receive shift register
Receive FIFO data register
Transmit shift register
Transmit FIFO data register
Serial mode register
Serial control register
Serial extension mode register

Serial status register
Bit rate register
Serial port register
FIFO control register
FIFO data count set register
Line status register

SCEMR