Renesas R5S72643 User Manual

 

 

Section 15   Serial Communication Interface with FIFO 

 

 

Page 718 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

5 PE  0 R/W

Parity 

Enable 

Selects whether to add a parity bit to transmit data and 
to check the parity of receive data, in asynchronous 
mode. In clock synchronous mode, a parity bit is neither 
added nor checked, regardless of the PE setting. 

0: Parity bit not added or checked 

1: Parity bit added and checked* 

Note:  *  When PE is set to 1, an even or odd parity 

bit is added to transmit data, depending on 
the parity mode (O/

E) setting. Receive data 

parity is checked according to the even/odd 
(O/

E) mode setting.  

4 O/

E 0 

R/W

Parity 

Mode 

Selects even or odd parity when parity bits are added 
and checked. The O/

E setting is used only in 

asynchronous mode and only when the parity enable bit 
(PE) is set to 1 to enable parity addition and checking. 
The O/

E setting is ignored in clock synchronous mode, 

or in asynchronous mode when parity addition and 
checking is disabled. 

0: Even parity*

1

 

1: Odd parity*

2

 

Notes:  1.  If even parity is selected, the parity bit is 

added to transmit data to make an even 
number of 1s in the transmitted character 
and parity bit combined. Receive data is 
checked to see if it has an even number of 
1s in the received character and parity bit 
combined. 

 

2.  If odd parity is selected, the parity bit is 

added to transmit data to make an odd 
number of 1s in the transmitted character 
and parity bit combined. Receive data is 
checked to see if it has an odd number of 1s 
in the received character and parity bit 
combined.