Renesas R5S72643 User Manual

 

Section 17   I

2

C Bus Interface 3 

R01UH0134EJ0400  Rev. 4.00  

 

Page 879 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when 
MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to 
figure 17.15. The reception procedure and operations in receive mode are described below. 

1.  Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) 

2.  When the transfer clock is output, set MST to 1 to start outputting the receive clock. 

3.  When the receive operation is completed, data is transferred from ICDRS to ICDRR and 

RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is 
continually output. The continuous reception is performed by reading ICDRR every time 
RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and 
AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR. 

4.  To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is 

fixed high after receiving the next byte data. 

 
Notes:  Follow the steps below to receive only one byte with MST = 1 specified. See figure 17.16 

for the operation timing. 

 

1.  Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) 

 

2.  Set MST = 1 while the RCVD bit in ICCR1 is 0. This causes the receive clock to be 

output. 

 

3.  Check if the BC2 bit in ICMR is set to 1 and then set the RCVD bit in ICCR1 to 1. 

This causes the SCL to be fixed to the high level after outputting one byte of the 
receive clock.