Renesas R5S72643 User Manual

 

Section 18   Serial Sound Interface 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 935 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

Yes

No

Yes

No

RUIEN = 1, ROIEN = 1, RIE = 1, 
REN = 1

REN = 0, 
RUIEN = 0, ROIEN = 0, 
IIEN = 1, RIE = 0

Start

Release from reset, 

set SSICR configuration bits.

Enable error interrupts 

and receive interrupts, 

then enable reception.

Wait for an interrupt.

Error interrupt?

Read data from receive 

data register.

Receive more data?

Disable receive operation, 

disable a data interrupt, 

disable an error interrupt, 

enable an idle interrupt.

Wait for an idle interrupt 

from this module

End

Define SCKD, SWSD, MUEN, 
DEL, PDTA, SDTA, SPDP, 
SWSP, SCKP, SWL, DWL, 
CHNL

Use SSI status register bits 

to realign data after 

underflow/overflow.

Set up the interrupt controller.