Renesas R5S72647 User Manual
Section 20 Controller Area Network
Page 1040 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(1) Time Trigger Control Register0 (TTCR0)
The Time Trigger Control Register0 is a 16-bit read/write register and provides functions to
control the operation of the Timer. When operating in Time Trigger Mode, please refer to section
20.4.3 (1), Time Triggered Transmission.
control the operation of the Timer. When operating in Time Trigger Mode, please refer to section
20.4.3 (1), Time Triggered Transmission.
TTCR0 (Address = H'080)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCR15 TCR14 TCR13 TCR12 TCR11
TCR6
TPSC5
TCR10
TPSC4 TPSC3 TPSC2 TPSC1 TPSC0
Bit:
Initial value:
R/W:
-
-
-
Bit 15 — Enable Timer: When this bit is set, the timer TCNTR is running. When this bit is
cleared, TCNTR and CCR are cleared.
cleared, TCNTR and CCR are cleared.
Bit15: TTCR0 15
Description
0
Timer and CCR are cleared and disabled (initial value)
1
Timer is running
Bit 14 — TimeStamp value: Specifies if the Timestamp for transmission and reception in
Mailboxes 15 to 0 must contain the Cycle Time (CYCTR) or the concatenation of CCR[5:0] +
CYCTR[15:6]. This feature is very useful for time triggered transmission to monitor Rx_Trigger.
Mailboxes 15 to 0 must contain the Cycle Time (CYCTR) or the concatenation of CCR[5:0] +
CYCTR[15:6]. This feature is very useful for time triggered transmission to monitor Rx_Trigger.
This register does not affect the TimeStamp for Mailboxes 30 and 31.
Bit14: TTCR0 14
Description
0
CYCTR[15:0] is used for the TimeStamp in Mailboxes 15 to 0 (initial value)
1
CCR[5:0] + CYCTR[15:6] is used for the TimeStamp in Mailboxes 15 to 0
Bit 13 — Cancellation by TCMR2: The messages in the transmission queue are cancelled by
setting TXCR, when both this bit and bit12 are set and compare match occurs when this module is
not in the Halt status, causing the setting of all TXCR bits with the corresponding TXPR bits set.
setting TXCR, when both this bit and bit12 are set and compare match occurs when this module is
not in the Halt status, causing the setting of all TXCR bits with the corresponding TXPR bits set.
Bit13: TTCR0 13
Description
0 Cancellation
by TCMR2 compare match is disabled (initial value)
1 Cancellation
by TCMR2 compare match is enabled