Renesas R5S72647 User Manual
Section 8 Cache
Page 212 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
8.2
Register Descriptions
Table 8.2 shows the register configuration of the cache.
Table 8.2
Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Cache control register 1
CCR1 R/W
H'00000000 H'FFFC1000
32
Cache control register 2
CCR2 R/W
H'00000000 H'FFFC1004
32
8.2.1
Cache Control Register 1 (CCR1)
The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all
instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF
bit controls disabling of all operand cache entries. The WT bit selects either write-through mode
or write-back mode for operand cache.
instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF
bit controls disabling of all operand cache entries. The WT bit selects either write-through mode
or write-back mode for operand cache.
Programs that change the contents of CCR1 should be placed in a cache-disabled space, and a
cache-enabled space should be accessed after reading the contents of CCR1.
cache-enabled space should be accessed after reading the contents of CCR1.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R/W
R
R
R/W
R
R
R
R
R/W
R
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ICF
-
-
ICE
-
-
-
-
OCF
-
WT
OCE