Renesas R5S72647 User Manual

 

 

Section 11   Multi-Function Timer Pulse Unit 2 
 

Page 446 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

5 

BFB 

0 

R/W 

Buffer Operation B 

Specifies whether TGRB is to operate in the normal 
way, or TGRB and TGRD are to be used together for 
buffer operation. When TGRD is used as a buffer 
register, TGRD input capture/output compare is not 
generated in a mode other than complementary PWM. 
In channels 1 and 2, which have no TGRD, bit 5 is 
reserved. It is always read as 0 and cannot be modified.

0: TGRB and TGRD operate normally 

1: TGRB and TGRD used together for buffer operation 

4 

BFA 

0 

R/W 

Buffer Operation A  

Specifies whether TGRA is to operate in the normal 
way, or TGRA and TGRC are to be used together for 
buffer operation. When TGRC is used as a buffer 
register, TGRC input capture/output compare is not 
generated in a mode other than complementary PWM. 
TGRC compare match is generated when in 
complementary PWM mode. When compare match for 
channel 4 occurs during the Tb period in 
complementary PWM mode, TGFC is set. Therefore, 
set the TGIEC bit in the timer interrupt enable register 4 
(TIER_4) to 0. 

In channels 1 and 2, which have no TGRC, bit 4 is 
reserved. It is always read as 0 and cannot be modified.

0: TGRA and TGRC operate normally 

1: TGRA and TGRC used together for buffer operation 

3 to 0 

MD[3:0] 

0000 

R/W 

Modes 0 to 3 

These bits are used to set the timer operating mode. 

See table 11.10 for details.