Renesas R5S72646 User Manual
Section 16 Renesas Serial Peripheral Interface
R01UH0134EJ0400 Rev. 4.00
Page 809 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Mode
Slave (SPI Operation)
Master (SPI Operation)
Transmit buffer empty detection
Supported
Supported
Receive buffer full detection
Supported
Supported
Overrun error detection
Supported
Not Supported
Mode fault error detection
Supported (MODFEN = 1)
Not supported
16.4.2
Pin Control
According to the MSTR bit in the control register (SPCR), this module can automatically switch
pin directions and output modes. Table 16.5 shows the relationship between pin states and bit
settings.
pin directions and output modes. Table 16.5 shows the relationship between pin states and bit
settings.
Table 16.5 Relationship between Pin States and Bit Settings
Mode Pin
Pin
State*
1
Master mode
(SPI operation)
(MSTR = 1)
(SPI operation)
(MSTR = 1)
RSPCK CMOS
output
SSL CMOS
output
MOSI CMOS
output
MISO Input
Slave mode
(SPI operation)
(MSTR = 0)
(SPI operation)
(MSTR = 0)
RSPCK Input
SSL Input
MOSI Input
MISO* CMOS
output/Hi-Z
Note: When SSL is at the non-active level or the SPE bit in SPCR is clear to 0, the pin state is
Hi-Z.
This module in master mode (SPI operation) determines MOSI signal values during the SSL
negation period (including the SSL retention period during a burst transfer) according to MOIFE
and MOIFV bit settings in SPPCR, as shown in table 16.6.
negation period (including the SSL retention period during a burst transfer) according to MOIFE
and MOIFV bit settings in SPPCR, as shown in table 16.6.
Table 16.6 MOSI Signal Value Determination during SSL Negation Period
MOIFE
MOIFV
MOSI Signal Value during SSL Negation Period
0
0, 1
Final data from previous transfer
1 0 Always
0
1 1 Always
1