Intel Xeon E7430 AD80583QH046003 Data Sheet
Product codes
AD80583QH046003
Intel® Xeon® Processor 7400 Series Datasheet
105
Features
7
Features
7.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The Intel® Xeon®
Processor 7400 Series samples its hardware configuration at reset, on the active-to-
inactive transition of RESET#. For specifics on these options, please refer to
Processor 7400 Series samples its hardware configuration at reset, on the active-to-
inactive transition of RESET#. For specifics on these options, please refer to
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor, for reset purposes, the processor does not distinguish between a “warm”
reset (PWRGOOD signal remains asserted) and a “power-on” reset.
configuration options cannot be changed except by another reset. All resets reconfigure
the processor, for reset purposes, the processor does not distinguish between a “warm”
reset (PWRGOOD signal remains asserted) and a “power-on” reset.
Notes:
1.
1.
Asserting this signal during RESET# will select the corresponding option.
2.
Address pins not identified in this table as configuration options should not be asserted during RESET#.
3.
Requires de-assertion of PWRGOOD.
Disabling of any of the cores within the Intel® Xeon® Processor 7400 Series must be
handled by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will
allow for the disabling of a single core per core pair within the Intel® Xeon® Processor
7400 Series package.
handled by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will
allow for the disabling of a single core per core pair within the Intel® Xeon® Processor
7400 Series package.
7.2
Clock Control and Low Power States
The Intel® Xeon® Processor 7400 Series supports the Extended HALT state (also
referred to as C1E) in addition to the HALT state and Stop-Grant state to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See
referred to as C1E) in addition to the HALT state and Stop-Grant state to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See
power states. The Extended HALT state is a lower power state than the HALT state or
Stop Grant state.
Stop Grant state.
The Extended HALT state must be enabled via the BIOS for the processor to
remain within its specifications. For processors that are already running at the
lowest bus to core frequency ratio for its nominal operating point, the processor will
transition to the HALT state instead of the Extended HALT state.
remain within its specifications. For processors that are already running at the
lowest bus to core frequency ratio for its nominal operating point, the processor will
transition to the HALT state instead of the Extended HALT state.
The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In
a multiprocessor system, all the STPCLK# signals are bussed together, thus all
processors are affected in unison. When the STPCLK# signal is asserted, the processor
enters the Stop Grant state, issuing a Stop Grant Special Bus Cycle (SBC) for each
processor. The chipset needs to account for a variable number of processors asserting
the Stop Grant SBC on the bus before allowing the processor to be transitioned into one
of the lower processor power states. Refer to the applicable chipset specification.
a multiprocessor system, all the STPCLK# signals are bussed together, thus all
processors are affected in unison. When the STPCLK# signal is asserted, the processor
enters the Stop Grant state, issuing a Stop Grant Special Bus Cycle (SBC) for each
processor. The chipset needs to account for a variable number of processors asserting
the Stop Grant SBC on the bus before allowing the processor to be transitioned into one
of the lower processor power states. Refer to the applicable chipset specification.
Table 7-1.
Power-On Configuration Option Pins
Configuration Option
Pin Name
Notes
Output tri state
SMI#
1,2,3
Execute BIST (Built-In Self Test)
A3#
1,2
Disable MCERR# observation
A9#
1,2
Disable BINIT# observation
A10#
1,2
Cluster ID
A[12:11]#
1,2
Disable bus parking
A15#
1,2