associated strobe (address or data) at nominal GTLREF_DATA_MID,
GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END. Source
synchronous data signals are referenced to the falling edge of their associated data
strobe. Source synchronous address signals are referenced to the rising and falling
edge of their associated address strobe. All source synchronous AGTL+ signal
timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END at the processor pads.

3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V

CROSS

. All

AGTL+ strobe signal timings are referenced at nominal GTLREF_DATA_MID,
GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor
pads.

4. All AC timings for the TAP signals are referenced to the TCK at 0.5 * V

at the

processor pins. All TAP signal timings (TMS, TDI, etc...) are referenced at 0.5 * V

at the processor pads.

5. All CMOS signal timings are referenced at 0.5 * V

at the processor pins.

6. All AC timings for the SMBus signals are referenced to the SM_CLK at 0.5 *

SM_VCC at the processor pins. All SMBus signal timings (SM_DAT, SM_CLK, etc.)
are referenced at

The circuit used to test the AC specification is shown in

Figure 2-7

Rise time is measured from (V

IL_MAX

- 0.15V) to (V

IH_MIN

+ 0.15V). Fall time is measured from

(0.9 * SM_VCC) to (V

IL_MAX

- 0.15V). DC parameters are specified in

Table 2-26

Minimum time allowed between request cycles.

Following a write transaction, an internal write cycle time of 10ms must be allowed before starting the next

transaction.

Figure 2-7. Electrical Test Circuit

48 ohms, 169 ps/in, 1200 mils

L = 1.475 nH

C = 0.85 pF

LOAD

AC Timings specified at this

point

Buffer