Intel E5440 AT80574KJ073N Data Sheet

40

The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END, 
GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard 
using high precision voltage divider circuits. Refer to the appropriate platform design 
guidelines for implementation details.

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

The tolerances for this specification have been stated generically to enable system designer to calculate the 

minimum values across the range of V

TT

.

3.

GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END is generated from V

TT

 

on the baseboard by a voltage divider of 1% resistors. The minimum and maximum specifications account 

for this resistor tolerance. Refer to the appropriate platform design guidelines for implementation details. 

The V

TT

 referred to in these specifications is the instantaneous V

TT

.

4.

R

TT

 is the on-die termination resistance measured at V

OL

 of the AGTL+ output driver. Measured at 

0.31*V

TT

. R

TT

 is connected to V

TT

 on die. Refer to processor I/O Buffer Models for I/V characteristics.

5.

COMP resistance must be provided on the system board with 1% resistors. See the applicable platform 

design guide for implementation details.

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to 

the falling edge of BCLK1.

3.

V

Havg

 is the statistical average of the V

H

 measured by the oscilloscope.

4.

Overshoot is defined as the absolute value of the maximum voltage.

5.

Undershoot is defined as the absolute value of the minimum voltage.

6.

Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback 

and the maximum Falling Edge Ringback.

GTLREF_DATA_MID, 

GTLREF_DATA_END

Data Bus Reference 

Voltage

0.98 * 

0.667 * V

TT

0.667 * 

V

TT

1.02*0.667 

* V

TT

V

2,  3

GTLREF_ADD_MID, 

GTLREF_ADD_END

Address Bus Reference 

Voltage

0.98 * 

0.667 * V

TT

0.667 * 

V

TT

1.02*0.667 

* V

TT

V

2,  3

R

TT

Termination 

Resistance (pull up)

45

50

55

Ω

4

COMP

COMP Resistance

49.4

49.9

50.4

Ω

5

V

L

Input Low Voltage

-0.150

0.0

0.150

V

V

H

Input High Voltage

0.660

0.710

0.850

V

V

CROSS(abs)

Absolute Crossing Point

0.250

0.350

0.550

V

2,9

V

CROSS(rel)

Relative Crossing Point

0.250 + 

0.5 * 

(V

Havg

 - 

0.700)

N/A

0.550 + 

0.5 * 

(V

Havg

 - 

0.700)

V

3,8,9,11

Δ

 VCROSS

Range of Crossing 

Points

N/A

N/A

0.140

V

V

OS

Overshoot

N/A

N/A

1.150

V

4

V

US

Undershoot

-0.300

N/A

N/A

V

5

V

RBM

Ringback Margin

0.200

N/A

N/A

V

6

V

TR

Threshold Region

V

CROSS

 - 

0.100

N/A

V

CROSS

 

+ 0.100

V

7

I

LI

Input Leakage Current

N/A

N/A

± 100

μA

10

ERRefclk-diffRrise
ERRefclk-diff-Fall

Differential Rising and 

falling edge rates

0.6

4

V/ns

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