Intel T1600 LF80537NF0281MN User Manual

34 

The Specification Clarifications listed in this section apply to the following documents: 

•  Mobile Intel

 Processor on .13 Micron Process in Micro-FCPGA Package Datasheet  

(Document Number  251308) 

All Specification Clarifications will be incorporated into a future version of the appropriate mobile Intel 
Celeron processor on 0.13 micron process in Micro-FCPGA Package documentation.  

 

The definition of DBI# signals will be clarified for Intel Pentium 4 Processors with Intel NetBurst 
Micro-architecture. The new definition will state:DBI[3:0]# are source synchronous and indicate the 
polarity of the D[63:0]# signals.  The DBI[3:0]# signals are activated when the data on the data bus is 
inverted. If more than half of the data bits, within a 16-bit group, would have been asserted electrically 
low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group. 

 

In the “Debugging and Performance Monitoring” section (Sections 15.8, 15.10.9 and 15.10.9.3) of the 
IA-32 Intel

 Architecture Software Developer’s Manual Volume 3: System Programming Guide, the 

Time-stamp Counter definition has been updated to include support for the future processors. This 
change will be incorporated in the next revision of the IA-32 Intel

Manual. 

The IA-32 architecture (beginning with the Pentium processor) defines a time-stamp counter mechanism 
that can be used to monitor and identify the relative time occurrence of processor events. The counter’s 
architecture includes the following components: 

•  TSC flag — A feature bit that indicates the availability of the time-stamp counter. The counter is 

available in an IA-32 processor implementation if the function CPUID.1:EDX.TSC[bit 4] = 1. 

•  IA32_TIME_STAMP_COUNTER MSR (called TSC MSR in P6 family and Pentium processors) 

— The MSR used as the counter. 

•  RDTSC instruction — An instruction used to read the time-stamp counter. 
•  TSD flag — A control register flag is used to enable or disable the time-stamp counter (enabled if 

CR4.TSD[bit 2] = 1). 

The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M, Pentium 4, and Intel 
Xeon processors) is a 64-bit counter that is set to 0 following a RESET of the processor. Following a