IBM Intel Xeon X5570 46D1357 User Manual
Product codes
46D1357
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
103
Register Description
2.15.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD
MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD
MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD
This register contains the ODT activation matrix for RANKS 4 to 7 for Reads.
2.15.21 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR
MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR
MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR
This register contains the ODT activation matrix for RANKS 0 to 3 for Writes.
2.15.22 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR
MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR
MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_WR
This register contains the ODT activation matrix for RANKS 4 to 7 for Writes.
Device:
4, 5, 6
Function:)0
Offset:
A8h
Access as a Dword
Bit
Type
Reset
Value
Description
31:24
RW
1
ODT_RD7. Bit patterns driven out onto ODT pins when Rank7 is read.
23:16
RW
1
ODT_RD6. Bit patterns driven out onto ODT pins when Rank6 is read.
15:8
RW
4
ODT_RD5. Bit patterns driven out onto ODT pins when Rank5 is read.
7:0
RW
4
ODT_RD4. Bit patterns driven out onto ODT pins when Rank4 is read.
Device:
4, 5, 6
Function: 0
Offset:
ACh
Access as a Dword
Bit
Type
Reset
Value
Description
31:24
RW
9
ODT_WR3. Bit patterns driven out onto ODT pins when Rank3 is written.
23:16
RW
5
ODT_WR2. Bit patterns driven out onto ODT pins when Rank2 is written.
15:8
RW
6
ODT_WR1. Bit patterns driven out onto ODT pins when Rank1 is written.
7:0
RW
5
ODT_WR0. Bit patterns driven out onto ODT pins when Rank0 is written.
Device:
4, 5, 6
Function: 0
Offset:
B0h
Access as a Dword
Bit
Type
Reset
Value
Description
31:24
RW
9
ODT_WR7. Bit patterns driven out onto ODT pins when Rank7 is written.
23:16
RW
5
ODT_WR6. Bit patterns driven out onto ODT pins when Rank6 is written.
15:8
RW
6
ODT_WR5. Bit patterns driven out onto ODT pins when Rank5 is written.
7:0
RW
5
ODT_WR4. Bit patterns driven out onto ODT pins when Rank4 is written