IBM Intel Xeon X5570 46D1357 User Manual

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Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

Channel Rank Limit Range Registers.

Channel Rank Interleave Way Range Registers. These registers allow the user to define 
the ranks and offsets that apply to the ranges defined by the LIMIT in the 
MC_RIR_LIMIT_CH registers. The mappings are as follows:

RIR_LIMIT_CH{chan}[0] -> RIR_WAY_CH{chan}[3:0] 

9:0

RW

0

LIMIT. This specifies the top of the range being mapped to the ranks specified 

in the MC_RIR_WAY_CH registers. The most significant bits of the lowest 

address in this range is one greater than the limit field in the RIR register with 

the next lower index. This field is compared against MA[37:28].