IBM Intel Xeon E5504 46D1351 User Manual
Product codes
46D1351
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
113
Register Description
2.17
Integrated Memory Controller Channel Rank
Registers
2.17.1
MC_RIR_LIMIT_CH0_0
MC_RIR_LIMIT_CH0_1
MC_RIR_LIMIT_CH0_2
MC_RIR_LIMIT_CH0_3
MC_RIR_LIMIT_CH0_4
MC_RIR_LIMIT_CH0_5
MC_RIR_LIMIT_CH0_6
MC_RIR_LIMIT_CH0_7
MC_RIR_LIMIT_CH1_0
MC_RIR_LIMIT_CH1_1
MC_RIR_LIMIT_CH1_2
MC_RIR_LIMIT_CH1_3
MC_RIR_LIMIT_CH1_4
MC_RIR_LIMIT_CH1_5
MC_RIR_LIMIT_CH1_6
MC_RIR_LIMIT_CH1_7
MC_RIR_LIMIT_CH2_0
MC_RIR_LIMIT_CH2_1
MC_RIR_LIMIT_CH2_2
MC_RIR_LIMIT_CH2_3
MC_RIR_LIMIT_CH2_4
MC_RIR_LIMIT_CH2_5
MC_RIR_LIMIT_CH2_6
MC_RIR_LIMIT_CH2_7
Device:
4
Function: 1
Offset:
80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch
Access as a Dword
Bit
Type
Reset
Value
Description
27
RW
0
DIVBY3. This bit indicates the rule is a 3 or 6 way interleave.
26:24
RW
0
REMOVED. These are the bits to be removed after offset subtraction. These
bits correspond to System Address [8,7,6].
23:0
RW
0
OFFSET. This value should be subtracted from the current system address to
create a contiguous address space within a channel. BITS 9:0 ARE RESERVED
AND MUST ALWAYS BE SET TO 0.