IBM Intel Xeon E5504 46D1351 User Manual

122

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

This register contains the 8 most significant bits [37:30] of the virtual temperature of 
each rank. The difference between the virtual temperature and the sensor temperature 
can be used to determine how fast fan speed should be increased. The value stored is 
right shifted one bit to the right with respect to the corresponding MC_Throttle_Offset 
register value. For example when When a rank throttle offset is set to 0x40, the value 
read from the corresponding in MC_RANK_VIRTUAL_TEMP register is 0x20. 

When there are more than 4 ranks attached to the channel, the thermal throttle logic is 
shared. 

This register contains the command portion of the DDR_THERM# functionality as 
described in the Intel® Xeon® Processor 5500 Series Datasheet, Volume 1 (i.e. what 
an assertion of the pin does).

31:24

RO

0

RANK3. Rank 3 virtual temperature.

23:16

RO

0

RANK2. Rank 2 virtual temperature.

15:8

RO

0

RANK1. Rank 1 virtual temperature.

7:0

RO

0

RANK0. Rank 0 virtual temperature.

3

RW

0

THROTTLE. Force throttling when DDR_THERM# pin is asserted.

2

RW

0

1

RW

0

DISABLE_EXTTS. Response to DDR_THERM# pin is disabled. ASSERTION and 

DEASSERTION fields in the register MC_DDR_THERM_STATUS are frozen.

0

RW1S

0

LOCK. When set, all bits in this register are RO and cannot be written. Reset 

will clear the lock.