IBM Intel Xeon E5504 46D1351 User Manual

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

41

DID

VID

00h

MC_CHANNEL_2_RANK_TIMING_A

80h

PCISTS

PCICMD

04h

MC_CHANNEL_2_RANK_TIMING_B

84h

CCR

RID

08h

MC_CHANNEL_2_BANK_TIMING

88h

HDR

0Ch

MC_CHANNEL_2_REFRESH_TIMING

8Ch

10h

MC_CHANNEL_2_CKE_TIMING

90h

14h

MC_CHANNEL_2_ZQ_TIMING

94h

18h

MC_CHANNEL_2_RCOMP_PARAMS

98h

1Ch

MC_CHANNEL_2_ODT_PARAMS1

9Ch

20h

MC_CHANNEL_2_ODT_PARAMS2

A0h

24h

MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD

A4h

28h

MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD

A8h

SID

SVID

2Ch

MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR

ACh

30h

MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_WR

B0h

34h

MC_CHANNEL_2_WAQ_PARAMS

B4h

38h

MC_CHANNEL_2_SCHEDULER_PARAMS

B8h

3Ch

MC_CHANNEL_2_MAINTENANCE_OPS

BCh

40h

MC_CHANNEL_2_TX_BG_SETTINGS

C0h

44h

C4h

48h

MC_CHANNEL_2_RX_BGF_SETTINGS

C8h

4Ch

MC_CHANNEL_2_EW_BGF_SETTINGS

CCh

MC_CHANNEL_2_DIMM_RESET_CMD

50h

MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS

D0h

MC_CHANNEL_2_DIMM_INIT_CMD

54h

MC_CHANNEL_2_ROUND_TRIP_LATENCY

D4h

MC_CHANNEL_2_DIMM_INIT_PARAMS

58h

MC_CHANNEL_2_PAGETABLE_PARAMS1

D8h

MC_CHANNEL_2_DIMM_INIT_STATUS

5Ch

DCh

MC_CHANNEL_2_DDR3CMD

60h

MC_TX_BG_CMD_DATA_RATIO_SETTING_CH2

E0h

64h

MC_TX_BG_CMD_OFFSET_SETTINGS_CH2

E4h

MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT

68h

MC_TX_BG_DATA_OFFSET_SETTINGS_CH2

E8h

6Ch

ECh

MC_CHANNEL_2_MRS_VALUE_0_1

70h

MC_CHANNEL_2_ADDR_MATCH

F0h

MC_CHANNEL_2_MRS_VALUE_2

74h

F4h

78h

MC_CHANNEL_2_ECC_ERROR_MASK

F8h

MC_CHANNEL_2_RANK_PRESENT

7Ch

MC_CHANNEL_2_ECC_ERROR_INJECT

FCh