IBM Intel Xeon E5504 46D1351 User Manual

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Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

Global register for PCIEXBAR address space.

SAD DRAM rules. Address Map for package determination.

39:20

RW

0

ADDRESS. Base address of PCIEXBAR. Must be naturally aligned to size; low 

order bits are ignored.

3:1

RW

0

SIZE. Size of the PCIEXBAR address space. (MAX bus number).
000: 256MB.
001: Reserved.
010: Reserved.
011: Reserved.
100: Reserved.
101: Reserved.
110: 64MB.
111: 128MB.

0

RW

0

ENABLE. Enable for PCIEXBAR address space. Editing size should not be done 

without also enabling range.

19:6

RW

-

LIMIT. DRAM rule top limit address. Must be strictly greater than previous rule, 

even if this rule is disabled, unless this rule and all following rules are disabled. 

Lower limit is the previous rule (or 0 if it is first rule). This field is compared 

against MA[39:26] in the memory address map.

2:1

RW

-

MODE. DRAM rule interleave mode. If a DRAM_RULE hits a 3 bit number is 

used to index into the corresponding interleave_list to determine which 

package the DRAM belongs to. This mode selects how that number is 

computed. 
00: Address bits {8,7,6}. 
01: Address bits {8,7,6} XORed with {18,17,16}. 
10: Address bit {6}, MOD3(Address[39..6]). (Note 6 is the high order bit) 
11: Reserved.

0

RW

0

ENABLE. Enable for DRAM rule. If Enabled Range between this rule and 

previous rule is Directed to HOME channel (unless overridden by other 

dedicated address range registers). If disabled, all accesses in this range are 

directed in MMIO to the IOH.